The invention relates to a thin film transistor (TFT) More particularly, the invention relates to a method of fabricating a thin film transistor (TFT).
Polysilicon thin film transistors have the characteristics of high carrier mobility, low temperature sensitivity and better driving capabilities and such they are applicable to high-speed elements. A liquid crystal display composed of switch elements of polysilicon thin film transistors has the characteristics of fast display, high luminosity, driving and control circuits made on a same board, higher reliability and lower cost. Therefore, polysilicon thin film transistor (TFT) liquid crystal displays have become a trend in development and manufacture.
When annealing amorphous silicon into polysilicon, the annealing temperature is higher than 600° C. For better crystallization, the annealing temperature must be raised to greater than 1000° C. which requires use of a quartz substrate. Quartz substrates, however, are expensive. Thus, less expensive glass substrates are typically substitutes for quartz substrates. Some low temperature polysilicon manufacturing processes (LTPS) for fabricating polysilicon on low-melting glass substrates have been developed. Some methods to reduce glass substrate damage caused by a heat process have also been proposed.
U.S. patent publication number 2004/0023446 discloses a method of manufacturing a thin film transistor and method of manufacturing a flat panel display, thin film transistor, and a flat panel display. An interlayer dielectric layer is formed on a gate electrode by spin coating to avoid disconnection. It is, however, necessary to add a heat process for burning the spin coated interlayer dielectric layer. The publication discloses simultaneously activating the impurity and burning the interlayer dielectric layer through a single heat treatment to reduce substrate damage.
FIG. 1 is a flowchart of a conventional method of forming a thin film transistor. The method comprises steps S30 to S41. First, in step S30, an amorphous silicon layer is formed over a substrate. In step S31, a heat treatment is performed to reduce the hydrogen atom concentration of the amorphous silicon layer. Then, in step S32, excimer laser annealing is performed to transfer the amorphous silicon layer into a polysilicon layer. In step S33, the polysilicon silicon layer is patterned to form an island-shaped polysilicon pattern. Next, step S34 covers an insulating layer over the island-shaped polysilicon pattern. Step S35 forms a gate electrode on the insulating layer. Then, step S36 forms an ion doped region in island-shaped polysilicon pattern. Step S37 performs a hydrogen plasma treatment to eliminate dangling bonds in the island-shaped polysilicon pattern. Next, step S38 forms an interlayer dielectric layer overlying the gate electrode. Step S39 performs a heat treatment to activate the ion doped region and simultaneously burn the interlayer dielectric layer. Step S40 then is selectively etches the interlayer dielectric layer to form an opening exposing the ion doped region. Next, in step S41, a metal layer is filled into the opening to form a source/drain electrode.
In step S37, dangling bonds at the grain boundary of island-shaped polysilicon pattern are reduced by heat treatment. Dangling bonds are, however, again generated spontaneously in channel region during subsequent heat processes such as step S39.
Two heat treatment steps are also respectively performed to reduce hydrogen atom concentration in the amorphous silicon layer and to transfer amorphous silicon into polysilicon, which may result in additional damage to the glass substrate.